The present invention relates generally to semiconductor processing and, more specifically, to methods of manufacturing semiconductor wafers employing one or more cleaning delay periods.
Scaling of complementary-metal-oxide-semiconductor (CMOS) technology is driven by the goals of increased integration density and improved performance. However, such scaling can be accompanied by increased penetration of impurities through-gate electrodes, especially as the dimensions of CMOS devices enter the deep-submicron regime. The performance of the scaled devices has also been hampered by excessive gate leakage current, resulting in exorbitant standby power consumption and rendering end-products commercially unacceptable.
Consequently, various nitridation methods have been proposed to replace at least portions of the silicon dioxide dielectric layers. For example, ultra-thin gate dielectric layers comprising stacked nitride and oxide layers have been proposed as viable alternatives to silicon dioxide. Such ultra-thin gate dielectric layers exhibit a high barrier to impurity diffusion and low gate leakage current density. Consequently, at least for deep-submicron CMOS devices and circuits, gate dielectric layers have been scaled towards configurations exhibiting a direct tunneling region. Many nitridation methods promise to further reduce leakage current levels and dielectric layer thicknesses while maintaining satisfactory effective oxide thicknesses far exceeding actual dielectric layer thicknesses.
Those skilled in the art recognize that semiconductor fabrication procedures typically include a large number of individual process steps, including numerous surface cleaning, material deposition, layer patterning and etching steps, often performed in a complex sequence resulting in the formation of 50–100 discrete layers and/or features. In view of the significant number of steps required to manufacture semiconductor devices, it is desirable to complete each step as quickly as possible without sacrificing manufacturing quality.
Accordingly, cluster tools configured to perform several consecutive process steps without transferring product wafers between separate process tools or workstations have played an integral role in the acceleration of semiconductor device fabrication schedules. For example, a first substrate having a surface previously cleaned in a cleaning chamber of a cluster tool may undergo oxidation in an oxide growth chamber while a second substrate is simultaneously cleaned in the cleaning chamber. However, the processes performed in each of the chambers of a cluster tool may not require the same amount of time for execution.
For example, continuing with the example above, the cleaning process may require only a fraction of the time required by the oxidation process. Consequently, the second substrate may be cleaned and ready for placement in the oxide growth chamber when the oxidation of the first substrate is only partially completed. However, as a result of the cleaning process, the second substrate may begin to oxidize within the cleaning chamber while the oxide growth chamber remains occupied by the first substrate. As a result, a thin layer of oxide may unintentionally form on the second substrate prior to the desired oxidation of the second substrate in the oxide growth chamber. Accordingly, the differences in the duration of individual process steps can render achieving a desired thickness and/or other electrical characteristic of a gate dielectric layer difficult, if not impossible.
Accordingly, what is needed in the art is a method of manufacturing a semiconductor device layer that addresses the above-discussed issues.